In the rapidly evolving landscape of semiconductor manufacturing, a groundbreaking development emerged from TSMC's presentation at the IEEE International Electron Devices Meeting (IEDM) in San Francisco. The focus was on their latest advancement in transistor technology, specifically the introduction of N2 technology, which represents TSMC's foray into a new transistor architecture called nanosheets, or gate-all-around (GAA) transistors. This innovation is set to revolutionize the capabilities of microchips, allowing for flexibility in design and functionality.
N2 technology is anticipated to enable up to 2,000 nanosheets on a single chip, a considerable increase from traditional designs. This flexible architecture allows different types of logic units to be constructed from varying nanosheet configurations, thereby enhancing the overall performance of semiconductors. TSMC, a giant in the semiconductor foundry industry, highlighted that compared to their cutting-edge N3 (3 nanometer) process, the N2 technology offers a 15% increase in speed, a 30% boost in energy efficiency, and a 15% enhancement in density.
The implications of this technological leap are profound. During the IEDM conference, TSMC’s Vice President of R&D and Advanced Technology, Geoffrey Yeap, remarked that N2 is the product of over four years of rigorous labor. This new approach contrasts with the FinFET (fin field-effect transistor) architecture currently dominating the industry, which primarily utilizes vertical silicon fins. In comparison, nanosheets consist of a stack of narrow silicon strips that can considerably improve current flow control within devices.
The flexibility of nanosheet technology not only controls current flow more effectively but also enables the creation of diverse devices by varying the widths of the sheets. While FinFET designs only offer diversity through the addition of more fins—such as one, two, or three—nanosheets facilitate nuanced design options that could correspond to any number of fins optimal for specific logic circuits, including fractional designs.
TSMC’s technology, named Nanoflex, embodies this adaptability, leading to a wide range of logical units crafted from 100 to 2,000 nanosheets on a single chip. The narrower devices will likely serve as general logic units, while those featuring broader nanosheets will be prime candidates for power-hungry CPU cores, therefore significantly enhancing computing capabilities.
An especially noteworthy advancement lies in the realm of SRAM (static random-access memory), a crucial component for processors. Traditionally, the scaling down of the six-transistor structure of SRAM has outpaced other logic circuits, creating a bottleneck in the advancement of memory efficiency. However, N2 appears poised to shatter this stagnation, yielding the densest SRAM units yet—capable of achieving 38 megabits per square millimeter, an 11% increase over TSMC’s previous N3 technology, which only saw a 6% improvement from its predecessor. Yeap emphasizes that “SRAM benefits from the inherent advantages of gate-all-around designs.”
As TSMC makes strides in transistor innovation, competitors like Intel are grappling with the complexities of maintaining a timeline for miniaturization. Intel’s research has indicated that scaling may take longer than initially anticipated. Ashish Agrawal, a silicon technology expert with Intel's component research team, explained to an audience of engineers that nanosheet structures are effectively the frontier of transistor technology.
Looking forward, future devices—such as Complementary FETs (CFETs), projected to emerge in the mid-2030s—will also be founded on nanosheet technologies. Thus, understanding their limitations becomes an increasingly critical endeavor, remarked Agrawal. Despite the challenges ahead, he stated, “We haven’t hit any roadblocks. It’s feasible; the evidence shows we’re creating superb transistors.”
Central to this and other advancements is gate length, a key scaling factor that determines the distance over which a gate controls current flow within a device. To reduce the minimum distance between devices in standard logic circuits—a distance dictated by historical terms known as Contact Poly-Silicon Pitch (CPP)—the scaling of gate lengths is critical. Agrawal noted that while scaling has predominantly been advanced through gate length reduction, difficulties may arise as gate lengths approach the 10-nanometer mark.
At this threshold, excessive current leakage through the device while it is off could present severe challenges. Agrawal added, “We’re considering pushing the process to lengths below 10 nanometers.” In pursuit of this ambition, Intel has altered the generic gate-all-around structure into a form featuring a single nanosheet, facilitating current flow across the single nanosheet when the device is active.
By thinning the nanosheet and modifying the surrounding materials, Intel's team successfully created devices with acceptable performance levels, achieving a gate length of just 6 nanometers and a nanosheet thickness of merely 3 nanometers. This advancement signifies a potential retreat from moving toward more exotic materials if current silicon-based devices can still deliver efficient results at these scales.
However, researchers anticipate that silicon gate-all-around devices will soon reach their limits in miniaturization. Consequently, Intel and other entities are exploring switching out silicon in nanosheets for two-dimensional semiconducting materials, like molybdenum disulfide. Nevertheless, the achievement of a 6-nanometer gate length suggests a temporary reprieve from this shift.
Sanjay Natarajan, Senior Vice President and Head of Technology Research at Intel Foundry, reaffirmed that there are currently no evident bottlenecks hindering progress. He indicates that “it’s feasible, and we’re demonstrating exceptional transistors with a channel length of 6 nanometers.”
During the IEDM session, TSMC’s Executive Vice President and Co-CEO, Dr. Wei K. Tsang, presented an engaging keynote speech. He elucidated the industry shifts from planar devices to FinFET designs, and more recently, to nanosheet technology for 2-nanometer gate-all-around devices. This journey mirrors advances in photolithographic techniques, evolving from immersion lithography to extreme ultraviolet (EUV) and multi-patterned EUV processes, while also highlighting the role of design technology co-optimization (DTCO).
Dr. Tsang underscored that beyond CFET, the ongoing quest for higher-performance, energy-efficient logic technologies necessitates accelerating the search for channel materials extending beyond silicon. Carbon nanotubes and transition metal dichalcogenides (TMDs) have drawn significant attention due to their unique physical and electronic characteristics.
In the domain of interconnects, Dr. Tsang discussed an innovative form of 2D material being explored as a superior substitute for copper. This emerging material exhibits lower thin-film resistivity than copper while maintaining reduced thickness, alleviating increases in line resistance often accompanying scaling geometries, thus enhancing overall chip performance.
Finally, he emphasized the importance of integrated systems technology (IV) in advancing 2D technologies. While pushing for miniaturization within individual dies to achieve better transistors and higher packing densities is critical, innovating beyond chip-level integration is equally vital for expanding into heterogeneous domains. The aim is not only to achieve localized improvements but also to exhibit significant advancements in overall system performance and efficiency.
Advanced silicon stacking and packaging technologies, including System on Integrated Chip (SoIC), InFO, and CoWoS, continue to dramatically shrink the interconnect spacing between chips, potentially boosting 3D interconnect density by six orders of magnitude, thus paving the way for an unprecedented future in microelectronics.